Zen 6: Ryzen X processors running at 6.5 GHz are said to be "100 percent" certain
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The well-known insider "Moore's Law Is Dead" claims to have learned from industry sources that AMD's upcoming Ryzen X processors, based on the Zen 6 architecture, will "100 percent" operate at speeds exceeding 6.5 GHz.
The YouTuber and insider Moore's Law Is Dead has released a new video about AMD's upcoming desktop processors, known as Ryzen X ("Olympic Ridge") and based on Zen 6 ("Morpheus"), and is now turning heads with unusually specific details and exceptionally high clock speeds. Owners of motherboards with the AM5 socket should follow these key details with particular interest, as the new Ryzen processors are ultimately intended to run on the existing platform.
AMD's next-generation Ryzen processors are expected to exceed 6.5 GHz
At "more than 6.5 GHz," the fastest Zen 6 processors would operate about 800 MHz faster than a Ryzen 9 9950X, whose boost clock tops out at 5.7 GHz. Moore's Law Is Dead specifically mentions this figure in its latest Youtube video and has now classified this information as "100 percent" confirmed. As early as late October 2025, the controversial insider speculated about AMD Ryzen X with clock speeds of up to 7 GHz. These exceptionally high clock speeds are now said to be "confirmed," according to MLID.
This would also put AMD at least 300 MHz ahead of Intel's Core i9-14900KS, which, at 6.2 GHz with the help of Intel Thermal Velocity Boost, currently holds the record for the highest factory-set clock speed of a desktop processor. The upcoming Ryzen processors are expected to far exceed that mark.
This leap is reportedly made possible by TSMC's 2-nm-class ("N2P") manufacturing process. The editorial teams at Overclock3D and 3DCenter.org have also picked up on the "rumor" and provided their analysis. We, too, agree with the preliminary assessment: such high clock speeds should be taken with a grain of salt for now, even though 6 GHz+ is certainly a realistic possibility.
It is widely considered a near certainty that AMD will be able to surpass the 5.7 GHz clock speed of the Ryzen 9 9950 and Ryzen 9 9950X3D simply due to significantly optimized manufacturing processes. While a boost clock of around 6.0 to 6.2 GHz is certainly realistic, 6.5 GHz and higher would be a real game-changer.
What to expect from Ryzen X with Zen 6
Ryzen X is expected to support up to 12 Zen 6 processor cores and 48 MB of traditional L3 cache per CCD ("Core Complex Die"), supplemented by 96 MB of stacked 3D V-Cache instead of the previous 64 MB. Since Ryzen X is expected to be expanded to up to 24 Zen 6 cores, two CCDs with double the L3 cache will be used accordingly.
| Ryzen 9000 Ryzen 9000X3D |
Ryzen X/10000 Ryzen X3D/10000X3D* |
|
|---|---|---|
| Code name | Granite Ridge Granite Ridge-X |
Olympic Ridge Olympic Ridge-X |
| Microarchitecture | Zen 5 (Nirvana) | Zen 6 (Morpheus) |
| Processor cores per CCD | 6 to 8 | 6 to 12 |
| Total number of processor cores | 6 to 16 | 6 to 24 |
| L3 cache per CCD | 16 to 32 MiByte | 24 to 48 MiByte |
| Total L3 cache | 32 to 64 MiByte** | 48 to 96 MiByte** |
| 3D V-Cache | 64 MiByte (1 CCD) | 96 MiByte (1 CCD), 192 MiByte (2 CCD) |
| L3 cache with 3D V-Cache | 96 to 128 MiByte*** | 144 MiByte (1 CCD), 288 MiByte (2 CCD)*** |
*) not officially confirmed. **) without 3D V-Cache. ***) with 3D V-Cache.
This means that a Ryzen X with 12 Zen 6 processor cores offers a total of 144 MiB of L3 cache on a single CCD, while a model with 24 Zen 6 compute units, on the other hand, will launch with two CCDs and 288 MiB of L3 cache. In addition to the 3D V-Cache, which may be stacked in two layers in the future, the classic L3 cache is also set to grow from the current 32 to 48 MiB with Zen 6.
- 6 Zen 6 processor cores on a single CCD
- 8 Zen 6 processor cores on a single CCD
- 10 Zen 6 processor cores on a single CCD
- 12 Zen 6 processor cores on a single CCD
- 16 Zen 6 processor cores on two CCDs (8+8)
- 20 Zen 6 processor cores on two CCDs (10+10)
- 24 Zen 6 processor cores on two CCDs (12+12)
Source: @9550pro
Thanks to the 2-nanometer manufacturing process ("TSMC N2"), the entire design is expected to be implemented on a chip area of just 76 mm², which would be smaller than that of a Zen 2 CCD with its two sets of four processor cores. That means a lot of transistors in a very small space. The I/O chiplet ("I/O Die") is expected to be manufactured using a 3-nanometer process ("TSMC N3P"), as the chipsets are also intended to be merely a refresh.
The IPC (instructions per cycle) is currently expected to increase by about 10 percent compared to Zen 5, which, combined with the significantly higher clock speeds, should result in a corresponding boost in performance.
Bugs in the B0 stepping: Market launch may not happen until 2027
A minor flaw in the existing B0 stepping could push back the Zen 6 launch to the first quarter of 2027. According to MLID, AMD has discovered an issue in the finished silicon that could impact performance.
The manufacturer now has three options: accept the flaw, mitigate it via microcode, or release a new stepping, which would delay the schedule. Given the competition from Intel Nova Lake, this decision is unlikely to be an easy one for AMD.
The manufacturer now has three options: accept the flaw, mitigate it via microcode, or release a new stepping, which would delay the schedule. Given the competition from Intel Nova Lake, this decision is unlikely to be an easy one for AMD. The editorial team at 3DCenter.org still considers a launch in the fourth quarter of 2026 possible, but now views the first quarter of 2027 as the more likely scenario.
Quelle: Moore's Law Is Dead via Overclock3D und 3DCenter.org
